1. Technical Field
The technical field relates to embedded capacitors made from thick-film, fired-on-foil dielectrics and electrodes in printed wiring boards [“PWB”] and semiconductor package substrates. More particularly, the technical field relates to creating process test capacitors simultaneously with the circuit capacitors to be embedded into PWB. The process test capacitors are test substitutes for embedded circuit capacitors to predict whether the capacitance, dissipation factor or insulation resistance of the circuit capacitors will be within acceptable specified ranges prior to and after embedment into PWB.
2. Related Art
As a known technology, embedding high capacitance density [“HCD”], thick-film capacitors in printed wiring boards and semiconductor package substrates promotes reduced circuit size and improved circuit performance. FIG. 1 illustrates a known method of making a multilayer printed wiring board having embedded thick-film, fired-on-foil capacitors. Although the formation of only two embedded circuit capacitors is shown, many capacitors may be formed on a foil by the known method.
FIG. 1A depicts the start of making an embedded thick-film circuit capacitor. A 1 oz (36 micron) copper foil 110 may be pretreated by applying a relatively thin (3-5 microns) underprint 112 of a copper paste to the capacitor side of the foil. Underprint 112 is dried at, for example, 120° C. for 10 minutes and then fired using copper thick-film firing conditions. The underprint is shown here as a surface coating. A recommended copper paste suitable for use as an underprint is EP 320, obtained from E.I. du Pont de Nemours and Company [“DuPont”].
With continuing reference to FIG. 1A, a thick-film capacitor dielectric material is screen printed onto the fired underprint 112, thereby forming a first printed pattern of capacitor dielectric layer 120. It is then dried at, for example 120° C. for 10 minutes. A suitable thick-film capacitor dielectric paste is EP 310, obtained from DuPont. After first thick-film dielectric layer 120 has been dried, second thick-film dielectric layer 125 (FIG. 1B) is screen printed over that and also dried.
FIG. 1C shows thick-film conductor layer 130 having been formed over second capacitor dielectric layer 125 as well as partially over foil 110. Conductive layer 130 may be formed by, for example, screen-printing the copper paste used to form underprint 112.
First and second capacitor dielectric layers 120 and 125 plus conductive material layer 130 are then co-fired under copper thick-film firing conditions to sinter the resulting structure together. During sintering, the two dielectric layers fuse together to form a single dielectric layer 128. FIG. 1D shows in plan view the resulting structure. At this stage, conductor layer 130 and foil 110 are connected and the capacitor is thus shorted. Therefore, the structure cannot function or be tested as a capacitor component. This is the foil stage.
FIG. 1E shows the patterned foil laminated with a suitable prepreg material 140 so that first electrode 130 faces the prepreg material. Another foil 160 may be applied to the opposite side of laminate prepreg material 140 to provide a surface for creating circuitry. After lamination, a photoresist is applied to foil 110 and foil 160, and the photoresists are imaged and developed.
Foils 110 and 160 are etched to form article 170 shown in FIG. 1F. Etching of the foil 160 creates copper pads 163 and 164. Etching of foil 110 creates trench 115. Trench 115 isolates second electrode 135 from conductor layer 130, connected to original foil 110, now 117. Second electrode 135, dielectric 128 and conductor layer 130—now first electrode 130 and connected to foil 117—form circuit capacitor 150. At this point, circuit capacitors 150 may be tested to ascertain if they meet electrical specifications by measuring the capacitance and/or other electrical properties between foil electrodes 135 and 117. This is the inner layer stage.
Referring to FIG. 1G, article 170 is laminated with other inner layer panels 175 to form multilayer structure 180. FIG. 1H shows vias 140 having been drilled to connect embedded circuit capacitors 150 to the outer layer copper foils, which have been etched to form copper pads 167, 168, etc., the whole article forming circuit board 190. Articles 180 and 190 may exhibit other layering designs than as shown in FIGS. 1G and 1H. For example, more layers may be added or microvias may be used to access the electrodes of the circuit capacitors.
The above known process has limits on circuit capacitor testing; specifically electrical properties of circuit capacitors cannot be tested until at least at the inner layer stage shown in FIG. 1F. However, by this stage several manufacturing steps have already occurred. Importantly, testing the electrical properties of the circuit capacitor at this stage is not even practicable when testing results in its damage or distortion. Thus, to end premature damage/distortion, testing of circuit capacitors is generally delayed until the finished printed circuit board stage in FIG. 1H.
However, this delay in testing fosters production waste and economic loss because certain properties of the circuit capacitors may have already been outside desired parameters at the foil stage at shown in FIG. 1D, or at the inner layer stage shown in FIG. 1F. The end result of the delay in testing is that, if upon testing at the conclusion of PWB fabrication, the electrical properties of the circuit capacitors are found outside the specified range, there is no alternative but to reject the entire board. It would be advantageous to know or predict whether certain electrical properties of the circuit capacitors are within desired ranges at earlier stages in the manufacture of the PWB This means that earlier testing that predicts circuit capacitors outside-of-specification promotes earlier discard of defective parts and reduces unnecessary economic loss.